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GNU Info File | 1996-07-15 | 35.2 KB | 925 lines |
- This is Info file as.info, produced by Makeinfo-1.55 from the input
- file ./as.texinfo.
-
- START-INFO-DIR-ENTRY
- * As: (as). The GNU assembler.
- END-INFO-DIR-ENTRY
-
- This file documents the GNU Assembler "as".
-
- Copyright (C) 1991, 92, 93, 94, 95, 1996 Free Software Foundation,
- Inc.
-
- Permission is granted to make and distribute verbatim copies of this
- manual provided the copyright notice and this permission notice are
- preserved on all copies.
-
- Permission is granted to copy and distribute modified versions of
- this manual under the conditions for verbatim copying, provided that
- the entire resulting derived work is distributed under the terms of a
- permission notice identical to this one.
-
- Permission is granted to copy and distribute translations of this
- manual into another language, under the above conditions for modified
- versions.
-
- File: as.info, Node: SH Opcodes, Prev: SH Directives, Up: SH-Dependent
-
- Opcodes
- -------
-
- For detailed information on the SH machine instruction set, see
- `SH-Microcomputer User's Manual' (Hitachi Micro Systems, Inc.).
-
- `as' implements all the standard SH opcodes. No additional
- pseudo-instructions are needed on this family. Note, however, that
- because `as' supports a simpler form of PC-relative addressing, you may
- simply write (for example)
-
- mov.l bar,r0
-
- where other assemblers might require an explicit displacement to `bar'
- from the program counter:
-
- mov.l @(DISP, PC)
-
- Here is a summary of SH opcodes:
-
- Legend:
- Rn a numbered register
- Rm another numbered register
- #imm immediate data
- disp displacement
- disp8 8-bit displacement
- disp12 12-bit displacement
-
- add #imm,Rn lds.l @Rn+,PR
- add Rm,Rn mac.w @Rm+,@Rn+
- addc Rm,Rn mov #imm,Rn
- addv Rm,Rn mov Rm,Rn
- and #imm,R0 mov.b Rm,@(R0,Rn)
- and Rm,Rn mov.b Rm,@-Rn
- and.b #imm,@(R0,GBR) mov.b Rm,@Rn
- bf disp8 mov.b @(disp,Rm),R0
- bra disp12 mov.b @(disp,GBR),R0
- bsr disp12 mov.b @(R0,Rm),Rn
- bt disp8 mov.b @Rm+,Rn
- clrmac mov.b @Rm,Rn
- clrt mov.b R0,@(disp,Rm)
- cmp/eq #imm,R0 mov.b R0,@(disp,GBR)
- cmp/eq Rm,Rn mov.l Rm,@(disp,Rn)
- cmp/ge Rm,Rn mov.l Rm,@(R0,Rn)
- cmp/gt Rm,Rn mov.l Rm,@-Rn
- cmp/hi Rm,Rn mov.l Rm,@Rn
- cmp/hs Rm,Rn mov.l @(disp,Rn),Rm
- cmp/pl Rn mov.l @(disp,GBR),R0
- cmp/pz Rn mov.l @(disp,PC),Rn
- cmp/str Rm,Rn mov.l @(R0,Rm),Rn
- div0s Rm,Rn mov.l @Rm+,Rn
- div0u mov.l @Rm,Rn
- div1 Rm,Rn mov.l R0,@(disp,GBR)
- exts.b Rm,Rn mov.w Rm,@(R0,Rn)
- exts.w Rm,Rn mov.w Rm,@-Rn
- extu.b Rm,Rn mov.w Rm,@Rn
- extu.w Rm,Rn mov.w @(disp,Rm),R0
- jmp @Rn mov.w @(disp,GBR),R0
- jsr @Rn mov.w @(disp,PC),Rn
- ldc Rn,GBR mov.w @(R0,Rm),Rn
- ldc Rn,SR mov.w @Rm+,Rn
- ldc Rn,VBR mov.w @Rm,Rn
- ldc.l @Rn+,GBR mov.w R0,@(disp,Rm)
- ldc.l @Rn+,SR mov.w R0,@(disp,GBR)
- ldc.l @Rn+,VBR mova @(disp,PC),R0
- lds Rn,MACH movt Rn
- lds Rn,MACL muls Rm,Rn
- lds Rn,PR mulu Rm,Rn
- lds.l @Rn+,MACH neg Rm,Rn
- lds.l @Rn+,MACL negc Rm,Rn
-
- nop stc VBR,Rn
- not Rm,Rn stc.l GBR,@-Rn
- or #imm,R0 stc.l SR,@-Rn
- or Rm,Rn stc.l VBR,@-Rn
- or.b #imm,@(R0,GBR) sts MACH,Rn
- rotcl Rn sts MACL,Rn
- rotcr Rn sts PR,Rn
- rotl Rn sts.l MACH,@-Rn
- rotr Rn sts.l MACL,@-Rn
- rte sts.l PR,@-Rn
- rts sub Rm,Rn
- sett subc Rm,Rn
- shal Rn subv Rm,Rn
- shar Rn swap.b Rm,Rn
- shll Rn swap.w Rm,Rn
- shll16 Rn tas.b @Rn
- shll2 Rn trapa #imm
- shll8 Rn tst #imm,R0
- shlr Rn tst Rm,Rn
- shlr16 Rn tst.b #imm,@(R0,GBR)
- shlr2 Rn xor #imm,R0
- shlr8 Rn xor Rm,Rn
- sleep xor.b #imm,@(R0,GBR)
- stc GBR,Rn xtrct Rm,Rn
- stc SR,Rn
-
- File: as.info, Node: Sparc-Dependent, Next: Z8000-Dependent, Prev: SH-Dependent, Up: Machine Dependencies
-
- SPARC Dependent Features
- ========================
-
- * Menu:
-
- * Sparc-Opts:: Options
- * Sparc-Float:: Floating Point
- * Sparc-Directives:: Sparc Machine Directives
-
- File: as.info, Node: Sparc-Opts, Next: Sparc-Float, Up: Sparc-Dependent
-
- Options
- -------
-
- The SPARC chip family includes several successive levels, using the
- same core instruction set, but including a few additional instructions
- at each level. There are exceptions to this however. For details on
- what instructions each variant supports, please see the chip's
- architecture reference manual.
-
- By default, `as' assumes the core instruction set (SPARC v6), but
- "bumps" the architecture level as needed: it switches to successively
- higher architectures as it encounters instructions that only exist in
- the higher levels.
-
- If not configured for SPARC v9 (`sparc64-*-*') GAS will not bump
- passed sparclite by default, an option must be passed to enable the v9
- instructions.
-
- GAS treats sparclite as being compatible with v8, unless an
- architecture is explicitly requested. SPARC v9 is always incompatible
- with sparclite.
-
- `-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite | -Av9 | -Av9a'
- Use one of the `-A' options to select one of the SPARC
- architectures explicitly. If you select an architecture
- explicitly, `as' reports a fatal error if it encounters an
- instruction or feature requiring a higher level.
-
- `-xarch=v8plus | -xarch=v8plusa'
- For compatibility with the Solaris v9 assembler. These options are
- equivalent to -Av9 and -Av9a, respectively.
-
- `-bump'
- Warn whenever it is necessary to switch to another level. If an
- architecture level is explicitly requested, GAS will not issue
- warnings until that level is reached, and will then bump the level
- as required (except between incompatible levels).
-
- File: as.info, Node: Sparc-Float, Next: Sparc-Directives, Prev: Sparc-Opts, Up: Sparc-Dependent
-
- Floating Point
- --------------
-
- The Sparc uses IEEE floating-point numbers.
-
- File: as.info, Node: Sparc-Directives, Prev: Sparc-Float, Up: Sparc-Dependent
-
- Sparc Machine Directives
- ------------------------
-
- The Sparc version of `as' supports the following additional machine
- directives:
-
- `.align'
- This must be followed by the desired alignment in bytes.
-
- `.common'
- This must be followed by a symbol name, a positive number, and
- `"bss"'. This behaves somewhat like `.comm', but the syntax is
- different.
-
- `.half'
- This is functionally identical to `.short'.
-
- `.proc'
- This directive is ignored. Any text following it on the same line
- is also ignored.
-
- `.reserve'
- This must be followed by a symbol name, a positive number, and
- `"bss"'. This behaves somewhat like `.lcomm', but the syntax is
- different.
-
- `.seg'
- This must be followed by `"text"', `"data"', or `"data1"'. It
- behaves like `.text', `.data', or `.data 1'.
-
- `.skip'
- This is functionally identical to the `.space' directive.
-
- `.word'
- On the Sparc, the `.word' directive produces 32 bit values,
- instead of the 16 bit values it produces on many other machines.
-
- `.xword'
- On the Sparc V9 processor, the `.xword' directive produces 64 bit
- values.
-
- File: as.info, Node: Z8000-Dependent, Next: Vax-Dependent, Prev: Sparc-Dependent, Up: Machine Dependencies
-
- Z8000 Dependent Features
- ========================
-
- The Z8000 as supports both members of the Z8000 family: the
- unsegmented Z8002, with 16 bit addresses, and the segmented Z8001 with
- 24 bit addresses.
-
- When the assembler is in unsegmented mode (specified with the
- `unsegm' directive), an address takes up one word (16 bit) sized
- register. When the assembler is in segmented mode (specified with the
- `segm' directive), a 24-bit address takes up a long (32 bit) register.
- *Note Assembler Directives for the Z8000: Z8000 Directives, for a list
- of other Z8000 specific assembler directives.
-
- * Menu:
-
- * Z8000 Options:: No special command-line options for Z8000
- * Z8000 Syntax:: Assembler syntax for the Z8000
- * Z8000 Directives:: Special directives for the Z8000
- * Z8000 Opcodes:: Opcodes
-
- File: as.info, Node: Z8000 Options, Next: Z8000 Syntax, Up: Z8000-Dependent
-
- Options
- -------
-
- `as' has no additional command-line options for the Zilog Z8000
- family.
-
- File: as.info, Node: Z8000 Syntax, Next: Z8000 Directives, Prev: Z8000 Options, Up: Z8000-Dependent
-
- Syntax
- ------
-
- * Menu:
-
- * Z8000-Chars:: Special Characters
- * Z8000-Regs:: Register Names
- * Z8000-Addressing:: Addressing Modes
-
- File: as.info, Node: Z8000-Chars, Next: Z8000-Regs, Up: Z8000 Syntax
-
- Special Characters
- ..................
-
- `!' is the line comment character.
-
- You can use `;' instead of a newline to separate statements.
-
- File: as.info, Node: Z8000-Regs, Next: Z8000-Addressing, Prev: Z8000-Chars, Up: Z8000 Syntax
-
- Register Names
- ..............
-
- The Z8000 has sixteen 16 bit registers, numbered 0 to 15. You can
- refer to different sized groups of registers by register number, with
- the prefix `r' for 16 bit registers, `rr' for 32 bit registers and `rq'
- for 64 bit registers. You can also refer to the contents of the first
- eight (of the sixteen 16 bit registers) by bytes. They are named `rNh'
- and `rNl'.
-
- *byte registers*
- r0l r0h r1h r1l r2h r2l r3h r3l
- r4h r4l r5h r5l r6h r6l r7h r7l
- *word registers*
- r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15
- *long word registers*
- rr0 rr2 rr4 rr6 rr8 rr10 rr12 rr14
- *quad word registers*
- rq0 rq4 rq8 rq12
-
- File: as.info, Node: Z8000-Addressing, Prev: Z8000-Regs, Up: Z8000 Syntax
-
- Addressing Modes
- ................
-
- as understands the following addressing modes for the Z8000:
-
- `rN'
- Register direct
-
- `@rN'
- Indirect register
-
- `ADDR'
- Direct: the 16 bit or 24 bit address (depending on whether the
- assembler is in segmented or unsegmented mode) of the operand is
- in the instruction.
-
- `address(rN)'
- Indexed: the 16 or 24 bit address is added to the 16 bit register
- to produce the final address in memory of the operand.
-
- `rN(#IMM)'
- Base Address: the 16 or 24 bit register is added to the 16 bit sign
- extended immediate displacement to produce the final address in
- memory of the operand.
-
- `rN(rM)'
- Base Index: the 16 or 24 bit register rN is added to the sign
- extended 16 bit index register rM to produce the final address in
- memory of the operand.
-
- `#XX'
- Immediate data XX.
-
- File: as.info, Node: Z8000 Directives, Next: Z8000 Opcodes, Prev: Z8000 Syntax, Up: Z8000-Dependent
-
- Assembler Directives for the Z8000
- ----------------------------------
-
- The Z8000 port of as includes these additional assembler directives,
- for compatibility with other Z8000 assemblers. As shown, these do not
- begin with `.' (unlike the ordinary as directives).
-
- `segm'
- Generates code for the segmented Z8001.
-
- `unsegm'
- Generates code for the unsegmented Z8002.
-
- `name'
- Synonym for `.file'
-
- `global'
- Synonym for `.global'
-
- `wval'
- Synonym for `.word'
-
- `lval'
- Synonym for `.long'
-
- `bval'
- Synonym for `.byte'
-
- `sval'
- Assemble a string. `sval' expects one string literal, delimited by
- single quotes. It assembles each byte of the string into
- consecutive addresses. You can use the escape sequence `%XX'
- (where XX represents a two-digit hexadecimal number) to represent
- the character whose ASCII value is XX. Use this feature to
- describe single quote and other characters that may not appear in
- string literals as themselves. For example, the C statement
- `char *a = "he said \"it's 50% off\"";' is represented in Z8000
- assembly language (shown with the assembler output in hex at the
- left) as
-
- 68652073 sval 'he said %22it%27s 50%25 off%22%00'
- 61696420
- 22697427
- 73203530
- 25206F66
- 662200
-
- `rsect'
- synonym for `.section'
-
- `block'
- synonym for `.space'
-
- `even'
- special case of `.align'; aligns output to even byte boundary.
-
- File: as.info, Node: Z8000 Opcodes, Prev: Z8000 Directives, Up: Z8000-Dependent
-
- Opcodes
- -------
-
- For detailed information on the Z8000 machine instruction set, see
- `Z8000 Technical Manual'.
-
- The following table summarizes the opcodes and their arguments:
-
- rs 16 bit source register
- rd 16 bit destination register
- rbs 8 bit source register
- rbd 8 bit destination register
- rrs 32 bit source register
- rrd 32 bit destination register
- rqs 64 bit source register
- rqd 64 bit destination register
- addr 16/24 bit address
- imm immediate data
-
- adc rd,rs clrb addr cpsir @rd,@rs,rr,cc
- adcb rbd,rbs clrb addr(rd) cpsirb @rd,@rs,rr,cc
- add rd,@rs clrb rbd dab rbd
- add rd,addr com @rd dbjnz rbd,disp7
- add rd,addr(rs) com addr dec @rd,imm4m1
- add rd,imm16 com addr(rd) dec addr(rd),imm4m1
- add rd,rs com rd dec addr,imm4m1
- addb rbd,@rs comb @rd dec rd,imm4m1
- addb rbd,addr comb addr decb @rd,imm4m1
- addb rbd,addr(rs) comb addr(rd) decb addr(rd),imm4m1
- addb rbd,imm8 comb rbd decb addr,imm4m1
- addb rbd,rbs comflg flags decb rbd,imm4m1
- addl rrd,@rs cp @rd,imm16 di i2
- addl rrd,addr cp addr(rd),imm16 div rrd,@rs
- addl rrd,addr(rs) cp addr,imm16 div rrd,addr
- addl rrd,imm32 cp rd,@rs div rrd,addr(rs)
- addl rrd,rrs cp rd,addr div rrd,imm16
- and rd,@rs cp rd,addr(rs) div rrd,rs
- and rd,addr cp rd,imm16 divl rqd,@rs
- and rd,addr(rs) cp rd,rs divl rqd,addr
- and rd,imm16 cpb @rd,imm8 divl rqd,addr(rs)
- and rd,rs cpb addr(rd),imm8 divl rqd,imm32
- andb rbd,@rs cpb addr,imm8 divl rqd,rrs
- andb rbd,addr cpb rbd,@rs djnz rd,disp7
- andb rbd,addr(rs) cpb rbd,addr ei i2
- andb rbd,imm8 cpb rbd,addr(rs) ex rd,@rs
- andb rbd,rbs cpb rbd,imm8 ex rd,addr
- bit @rd,imm4 cpb rbd,rbs ex rd,addr(rs)
- bit addr(rd),imm4 cpd rd,@rs,rr,cc ex rd,rs
- bit addr,imm4 cpdb rbd,@rs,rr,cc exb rbd,@rs
- bit rd,imm4 cpdr rd,@rs,rr,cc exb rbd,addr
- bit rd,rs cpdrb rbd,@rs,rr,cc exb rbd,addr(rs)
- bitb @rd,imm4 cpi rd,@rs,rr,cc exb rbd,rbs
- bitb addr(rd),imm4 cpib rbd,@rs,rr,cc ext0e imm8
- bitb addr,imm4 cpir rd,@rs,rr,cc ext0f imm8
- bitb rbd,imm4 cpirb rbd,@rs,rr,cc ext8e imm8
- bitb rbd,rs cpl rrd,@rs ext8f imm8
- bpt cpl rrd,addr exts rrd
- call @rd cpl rrd,addr(rs) extsb rd
- call addr cpl rrd,imm32 extsl rqd
- call addr(rd) cpl rrd,rrs halt
- calr disp12 cpsd @rd,@rs,rr,cc in rd,@rs
- clr @rd cpsdb @rd,@rs,rr,cc in rd,imm16
- clr addr cpsdr @rd,@rs,rr,cc inb rbd,@rs
- clr addr(rd) cpsdrb @rd,@rs,rr,cc inb rbd,imm16
- clr rd cpsi @rd,@rs,rr,cc inc @rd,imm4m1
- clrb @rd cpsib @rd,@rs,rr,cc inc addr(rd),imm4m1
- inc addr,imm4m1 ldb rbd,rs(rx) mult rrd,addr(rs)
- inc rd,imm4m1 ldb rd(imm16),rbs mult rrd,imm16
- incb @rd,imm4m1 ldb rd(rx),rbs mult rrd,rs
- incb addr(rd),imm4m1 ldctl ctrl,rs multl rqd,@rs
- incb addr,imm4m1 ldctl rd,ctrl multl rqd,addr
- incb rbd,imm4m1 ldd @rs,@rd,rr multl rqd,addr(rs)
- ind @rd,@rs,ra lddb @rs,@rd,rr multl rqd,imm32
- indb @rd,@rs,rba lddr @rs,@rd,rr multl rqd,rrs
- inib @rd,@rs,ra lddrb @rs,@rd,rr neg @rd
- inibr @rd,@rs,ra ldi @rd,@rs,rr neg addr
- iret ldib @rd,@rs,rr neg addr(rd)
- jp cc,@rd ldir @rd,@rs,rr neg rd
- jp cc,addr ldirb @rd,@rs,rr negb @rd
- jp cc,addr(rd) ldk rd,imm4 negb addr
- jr cc,disp8 ldl @rd,rrs negb addr(rd)
- ld @rd,imm16 ldl addr(rd),rrs negb rbd
- ld @rd,rs ldl addr,rrs nop
- ld addr(rd),imm16 ldl rd(imm16),rrs or rd,@rs
- ld addr(rd),rs ldl rd(rx),rrs or rd,addr
- ld addr,imm16 ldl rrd,@rs or rd,addr(rs)
- ld addr,rs ldl rrd,addr or rd,imm16
- ld rd(imm16),rs ldl rrd,addr(rs) or rd,rs
- ld rd(rx),rs ldl rrd,imm32 orb rbd,@rs
- ld rd,@rs ldl rrd,rrs orb rbd,addr
- ld rd,addr ldl rrd,rs(imm16) orb rbd,addr(rs)
- ld rd,addr(rs) ldl rrd,rs(rx) orb rbd,imm8
- ld rd,imm16 ldm @rd,rs,n orb rbd,rbs
- ld rd,rs ldm addr(rd),rs,n out @rd,rs
- ld rd,rs(imm16) ldm addr,rs,n out imm16,rs
- ld rd,rs(rx) ldm rd,@rs,n outb @rd,rbs
- lda rd,addr ldm rd,addr(rs),n outb imm16,rbs
- lda rd,addr(rs) ldm rd,addr,n outd @rd,@rs,ra
- lda rd,rs(imm16) ldps @rs outdb @rd,@rs,rba
- lda rd,rs(rx) ldps addr outib @rd,@rs,ra
- ldar rd,disp16 ldps addr(rs) outibr @rd,@rs,ra
- ldb @rd,imm8 ldr disp16,rs pop @rd,@rs
- ldb @rd,rbs ldr rd,disp16 pop addr(rd),@rs
- ldb addr(rd),imm8 ldrb disp16,rbs pop addr,@rs
- ldb addr(rd),rbs ldrb rbd,disp16 pop rd,@rs
- ldb addr,imm8 ldrl disp16,rrs popl @rd,@rs
- ldb addr,rbs ldrl rrd,disp16 popl addr(rd),@rs
- ldb rbd,@rs mbit popl addr,@rs
- ldb rbd,addr mreq rd popl rrd,@rs
- ldb rbd,addr(rs) mres push @rd,@rs
- ldb rbd,imm8 mset push @rd,addr
- ldb rbd,rbs mult rrd,@rs push @rd,addr(rs)
- ldb rbd,rs(imm16) mult rrd,addr push @rd,imm16
- push @rd,rs set addr,imm4 subl rrd,imm32
- pushl @rd,@rs set rd,imm4 subl rrd,rrs
- pushl @rd,addr set rd,rs tcc cc,rd
- pushl @rd,addr(rs) setb @rd,imm4 tccb cc,rbd
- pushl @rd,rrs setb addr(rd),imm4 test @rd
- res @rd,imm4 setb addr,imm4 test addr
- res addr(rd),imm4 setb rbd,imm4 test addr(rd)
- res addr,imm4 setb rbd,rs test rd
- res rd,imm4 setflg imm4 testb @rd
- res rd,rs sinb rbd,imm16 testb addr
- resb @rd,imm4 sinb rd,imm16 testb addr(rd)
- resb addr(rd),imm4 sind @rd,@rs,ra testb rbd
- resb addr,imm4 sindb @rd,@rs,rba testl @rd
- resb rbd,imm4 sinib @rd,@rs,ra testl addr
- resb rbd,rs sinibr @rd,@rs,ra testl addr(rd)
- resflg imm4 sla rd,imm8 testl rrd
- ret cc slab rbd,imm8 trdb @rd,@rs,rba
- rl rd,imm1or2 slal rrd,imm8 trdrb @rd,@rs,rba
- rlb rbd,imm1or2 sll rd,imm8 trib @rd,@rs,rbr
- rlc rd,imm1or2 sllb rbd,imm8 trirb @rd,@rs,rbr
- rlcb rbd,imm1or2 slll rrd,imm8 trtdrb @ra,@rb,rbr
- rldb rbb,rba sout imm16,rs trtib @ra,@rb,rr
- rr rd,imm1or2 soutb imm16,rbs trtirb @ra,@rb,rbr
- rrb rbd,imm1or2 soutd @rd,@rs,ra trtrb @ra,@rb,rbr
- rrc rd,imm1or2 soutdb @rd,@rs,rba tset @rd
- rrcb rbd,imm1or2 soutib @rd,@rs,ra tset addr
- rrdb rbb,rba soutibr @rd,@rs,ra tset addr(rd)
- rsvd36 sra rd,imm8 tset rd
- rsvd38 srab rbd,imm8 tsetb @rd
- rsvd78 sral rrd,imm8 tsetb addr
- rsvd7e srl rd,imm8 tsetb addr(rd)
- rsvd9d srlb rbd,imm8 tsetb rbd
- rsvd9f srll rrd,imm8 xor rd,@rs
- rsvdb9 sub rd,@rs xor rd,addr
- rsvdbf sub rd,addr xor rd,addr(rs)
- sbc rd,rs sub rd,addr(rs) xor rd,imm16
- sbcb rbd,rbs sub rd,imm16 xor rd,rs
- sc imm8 sub rd,rs xorb rbd,@rs
- sda rd,rs subb rbd,@rs xorb rbd,addr
- sdab rbd,rs subb rbd,addr xorb rbd,addr(rs)
- sdal rrd,rs subb rbd,addr(rs) xorb rbd,imm8
- sdl rd,rs subb rbd,imm8 xorb rbd,rbs
- sdlb rbd,rs subb rbd,rbs xorb rbd,rbs
- sdll rrd,rs subl rrd,@rs
- set @rd,imm4 subl rrd,addr
- set addr(rd),imm4 subl rrd,addr(rs)
-
- File: as.info, Node: Vax-Dependent, Prev: Z8000-Dependent, Up: Machine Dependencies
-
- VAX Dependent Features
- ======================
-
- * Menu:
-
- * VAX-Opts:: VAX Command-Line Options
- * VAX-float:: VAX Floating Point
- * VAX-directives:: Vax Machine Directives
- * VAX-opcodes:: VAX Opcodes
- * VAX-branch:: VAX Branch Improvement
- * VAX-operands:: VAX Operands
- * VAX-no:: Not Supported on VAX
-
- File: as.info, Node: VAX-Opts, Next: VAX-float, Up: Vax-Dependent
-
- VAX Command-Line Options
- ------------------------
-
- The Vax version of `as' accepts any of the following options, gives
- a warning message that the option was ignored and proceeds. These
- options are for compatibility with scripts designed for other people's
- assemblers.
-
- ``-D' (Debug)'
- ``-S' (Symbol Table)'
- ``-T' (Token Trace)'
- These are obsolete options used to debug old assemblers.
-
- ``-d' (Displacement size for JUMPs)'
- This option expects a number following the `-d'. Like options
- that expect filenames, the number may immediately follow the `-d'
- (old standard) or constitute the whole of the command line
- argument that follows `-d' (GNU standard).
-
- ``-V' (Virtualize Interpass Temporary File)'
- Some other assemblers use a temporary file. This option commanded
- them to keep the information in active memory rather than in a
- disk file. `as' always does this, so this option is redundant.
-
- ``-J' (JUMPify Longer Branches)'
- Many 32-bit computers permit a variety of branch instructions to
- do the same job. Some of these instructions are short (and fast)
- but have a limited range; others are long (and slow) but can
- branch anywhere in virtual memory. Often there are 3 flavors of
- branch: short, medium and long. Some other assemblers would emit
- short and medium branches, unless told by this option to emit
- short and long branches.
-
- ``-t' (Temporary File Directory)'
- Some other assemblers may use a temporary file, and this option
- takes a filename being the directory to site the temporary file.
- Since `as' does not use a temporary disk file, this option makes
- no difference. `-t' needs exactly one filename.
-
- The Vax version of the assembler accepts two options when compiled
- for VMS. They are `-h', and `-+'. The `-h' option prevents `as' from
- modifying the symbol-table entries for symbols that contain lowercase
- characters (I think). The `-+' option causes `as' to print warning
- messages if the FILENAME part of the object file, or any symbol name is
- larger than 31 characters. The `-+' option also inserts some code
- following the `_main' symbol so that the object file is compatible with
- Vax-11 "C".
-
- File: as.info, Node: VAX-float, Next: VAX-directives, Prev: VAX-Opts, Up: Vax-Dependent
-
- VAX Floating Point
- ------------------
-
- Conversion of flonums to floating point is correct, and compatible
- with previous assemblers. Rounding is towards zero if the remainder is
- exactly half the least significant bit.
-
- `D', `F', `G' and `H' floating point formats are understood.
-
- Immediate floating literals (*e.g.* `S`$6.9') are rendered
- correctly. Again, rounding is towards zero in the boundary case.
-
- The `.float' directive produces `f' format numbers. The `.double'
- directive produces `d' format numbers.
-
- File: as.info, Node: VAX-directives, Next: VAX-opcodes, Prev: VAX-float, Up: Vax-Dependent
-
- Vax Machine Directives
- ----------------------
-
- The Vax version of the assembler supports four directives for
- generating Vax floating point constants. They are described in the
- table below.
-
- `.dfloat'
- This expects zero or more flonums, separated by commas, and
- assembles Vax `d' format 64-bit floating point constants.
-
- `.ffloat'
- This expects zero or more flonums, separated by commas, and
- assembles Vax `f' format 32-bit floating point constants.
-
- `.gfloat'
- This expects zero or more flonums, separated by commas, and
- assembles Vax `g' format 64-bit floating point constants.
-
- `.hfloat'
- This expects zero or more flonums, separated by commas, and
- assembles Vax `h' format 128-bit floating point constants.
-
- File: as.info, Node: VAX-opcodes, Next: VAX-branch, Prev: VAX-directives, Up: Vax-Dependent
-
- VAX Opcodes
- -----------
-
- All DEC mnemonics are supported. Beware that `case...' instructions
- have exactly 3 operands. The dispatch table that follows the `case...'
- instruction should be made with `.word' statements. This is compatible
- with all unix assemblers we know of.
-
- File: as.info, Node: VAX-branch, Next: VAX-operands, Prev: VAX-opcodes, Up: Vax-Dependent
-
- VAX Branch Improvement
- ----------------------
-
- Certain pseudo opcodes are permitted. They are for branch
- instructions. They expand to the shortest branch instruction that
- reaches the target. Generally these mnemonics are made by substituting
- `j' for `b' at the start of a DEC mnemonic. This feature is included
- both for compatibility and to help compilers. If you do not need this
- feature, avoid these opcodes. Here are the mnemonics, and the code
- they can expand into.
-
- `jbsb'
- `Jsb' is already an instruction mnemonic, so we chose `jbsb'.
- (byte displacement)
- `bsbb ...'
-
- (word displacement)
- `bsbw ...'
-
- (long displacement)
- `jsb ...'
-
- `jbr'
- `jr'
- Unconditional branch.
- (byte displacement)
- `brb ...'
-
- (word displacement)
- `brw ...'
-
- (long displacement)
- `jmp ...'
-
- `jCOND'
- COND may be any one of the conditional branches `neq', `nequ',
- `eql', `eqlu', `gtr', `geq', `lss', `gtru', `lequ', `vc', `vs',
- `gequ', `cc', `lssu', `cs'. COND may also be one of the bit tests
- `bs', `bc', `bss', `bcs', `bsc', `bcc', `bssi', `bcci', `lbs',
- `lbc'. NOTCOND is the opposite condition to COND.
- (byte displacement)
- `bCOND ...'
-
- (word displacement)
- `bNOTCOND foo ; brw ... ; foo:'
-
- (long displacement)
- `bNOTCOND foo ; jmp ... ; foo:'
-
- `jacbX'
- X may be one of `b d f g h l w'.
- (word displacement)
- `OPCODE ...'
-
- (long displacement)
- OPCODE ..., foo ;
- brb bar ;
- foo: jmp ... ;
- bar:
-
- `jaobYYY'
- YYY may be one of `lss leq'.
-
- `jsobZZZ'
- ZZZ may be one of `geq gtr'.
- (byte displacement)
- `OPCODE ...'
-
- (word displacement)
- OPCODE ..., foo ;
- brb bar ;
- foo: brw DESTINATION ;
- bar:
-
- (long displacement)
- OPCODE ..., foo ;
- brb bar ;
- foo: jmp DESTINATION ;
- bar:
-
- `aobleq'
- `aoblss'
- `sobgeq'
- `sobgtr'
- (byte displacement)
- `OPCODE ...'
-
- (word displacement)
- OPCODE ..., foo ;
- brb bar ;
- foo: brw DESTINATION ;
- bar:
-
- (long displacement)
- OPCODE ..., foo ;
- brb bar ;
- foo: jmp DESTINATION ;
- bar:
-
- File: as.info, Node: VAX-operands, Next: VAX-no, Prev: VAX-branch, Up: Vax-Dependent
-
- VAX Operands
- ------------
-
- The immediate character is `$' for Unix compatibility, not `#' as
- DEC writes it.
-
- The indirect character is `*' for Unix compatibility, not `@' as DEC
- writes it.
-
- The displacement sizing character is ``' (an accent grave) for Unix
- compatibility, not `^' as DEC writes it. The letter preceding ``' may
- have either case. `G' is not understood, but all other letters (`b i l
- s w') are understood.
-
- Register names understood are `r0 r1 r2 ... r15 ap fp sp pc'. Upper
- and lower case letters are equivalent.
-
- For instance
- tstb *w`$4(r5)
-
- Any expression is permitted in an operand. Operands are comma
- separated.
-
- File: as.info, Node: VAX-no, Prev: VAX-operands, Up: Vax-Dependent
-
- Not Supported on VAX
- --------------------
-
- Vax bit fields can not be assembled with `as'. Someone can add the
- required code if they really need it.
-
- File: as.info, Node: Acknowledgements, Next: Index, Prev: Machine Dependencies, Up: Top
-
- Acknowledgements
- ****************
-
- If you have contributed to `as' and your name isn't listed here, it
- is not meant as a slight. We just don't know about it. Send mail to
- the maintainer, and we'll correct the situation. Currently the
- maintainer is Ken Raeburn (email address `raeburn@cygnus.com').
-
- Dean Elsner wrote the original GNU assembler for the VAX.(1)
-
- Jay Fenlason maintained GAS for a while, adding support for
- GDB-specific debug information and the 68k series machines, most of the
- preprocessing pass, and extensive changes in `messages.c',
- `input-file.c', `write.c'.
-
- K. Richard Pixley maintained GAS for a while, adding various
- enhancements and many bug fixes, including merging support for several
- processors, breaking GAS up to handle multiple object file format back
- ends (including heavy rewrite, testing, an integration of the coff and
- b.out back ends), adding configuration including heavy testing and
- verification of cross assemblers and file splits and renaming,
- converted GAS to strictly ANSI C including full prototypes, added
- support for m680[34]0 and cpu32, did considerable work on i960
- including a COFF port (including considerable amounts of reverse
- engineering), a SPARC opcode file rewrite, DECstation, rs6000, and
- hp300hpux host ports, updated "know" assertions and made them work,
- much other reorganization, cleanup, and lint.
-
- Ken Raeburn wrote the high-level BFD interface code to replace most
- of the code in format-specific I/O modules.
-
- The original VMS support was contributed by David L. Kashtan. Eric
- Youngdale has done much work with it since.
-
- The Intel 80386 machine description was written by Eliot Dresselhaus.
-
- Minh Tran-Le at IntelliCorp contributed some AIX 386 support.
-
- The Motorola 88k machine description was contributed by Devon Bowen
- of Buffalo University and Torbjorn Granlund of the Swedish Institute of
- Computer Science.
-
- Keith Knowles at the Open Software Foundation wrote the original
- MIPS back end (`tc-mips.c', `tc-mips.h'), and contributed Rose format
- support (which hasn't been merged in yet). Ralph Campbell worked with
- the MIPS code to support a.out format.
-
- Support for the Zilog Z8k and Hitachi H8/300 and H8/500 processors
- (tc-z8k, tc-h8300, tc-h8500), and IEEE 695 object file format
- (obj-ieee), was written by Steve Chamberlain of Cygnus Support. Steve
- also modified the COFF back end to use BFD for some low-level
- operations, for use with the H8/300 and AMD 29k targets.
-
- John Gilmore built the AMD 29000 support, added `.include' support,
- and simplified the configuration of which versions accept which
- directives. He updated the 68k machine description so that Motorola's
- opcodes always produced fixed-size instructions (e.g. `jsr'), while
- synthetic instructions remained shrinkable (`jbsr'). John fixed many
- bugs, including true tested cross-compilation support, and one bug in
- relaxation that took a week and required the proverbial one-bit fix.
-
- Ian Lance Taylor of Cygnus Support merged the Motorola and MIT
- syntax for the 68k, completed support for some COFF targets (68k, i386
- SVR3, and SCO Unix), added support for MIPS ECOFF and ELF targets,
- wrote the initial RS/6000 and PowerPC assembler, and made a few other
- minor patches.
-
- Steve Chamberlain made `as' able to generate listings.
-
- Hewlett-Packard contributed support for the HP9000/300.
-
- Jeff Law wrote GAS and BFD support for the native HPPA object format
- (SOM) along with a fairly extensive HPPA testsuite (for both SOM and
- ELF object formats). This work was supported by both the Center for
- Software Science at the University of Utah and Cygnus Support.
-
- Support for ELF format files has been worked on by Mark Eichin of
- Cygnus Support (original, incomplete implementation for SPARC), Pete
- Hoogenboom and Jeff Law at the University of Utah (HPPA mainly),
- Michael Meissner of the Open Software Foundation (i386 mainly), and Ken
- Raeburn of Cygnus Support (sparc, and some initial 64-bit support).
-
- Richard Henderson rewrote the Alpha assembler.
-
- Several engineers at Cygnus Support have also provided many small
- bug fixes and configuration enhancements.
-
- Many others have contributed large or small bugfixes and
- enhancements. If you have contributed significant work and are not
- mentioned on this list, and want to be, let us know. Some of the
- history has been lost; we are not intentionally leaving anyone out.
-
- ---------- Footnotes ----------
-
- (1) Any more details?
-
-